Nehalem

At the IDF 2008 (Intel developer forum) most people will remember it as the year of Son of Conroe: Nehalem. While the news of the new Nehalem chip has been around for a while now, IDF 2008 is when Intel first talked about it in earnest and what it could mean for Intel and its competitors.

Nehalem was purely a codename for the Intel product development, but at IDF Intel finally gave the chip its own unique designation, and the title under which people will recognise the chip in a shop: Core i7. As with all Intel chip products, one name will cover a multitude of desktop offerings, ranging from dual-core desktop parts to eight core monsters. For the server products, the 'Nehalem' title is being retained, with the first chips dubbed Nehalem-ES. Both this and the first high-end Core i7 products will appear at the end of this year, to be followed in 2009 by Nehalem­-EX (EX for Expandable) server components, and the consumer desktop parts 'Lynnfield' and  'Havendale'. it has also managed to plan some notebook derivatives, which are codenamed 'Clarksfield' and 'Auburndale'. If you weren't counting, that's seven new chips over three market sectors in less than six months.

So how do these chips differ from the Core 2 Duo and Quad processors we're now familiar with? On one level they're not substantially different, being built on the same 45nm process as the Penryn Core 2 Duo chips. On another level there are substantially differences with Nehalem having both integrated memory controller and Quick Path Interconnect links (QPI).
Nehalem is a fully integrated quad-core device, with an inclusive and shared last level cache. A central queue acts as a crossbar and arbiter between the four cores and the ‘uncore’ region of Nehalem, which includes the L3 cache, integrated memory controller and QPI links. From a performance perspective, the inclusive L3 cache is the ideal configuration since it keeps the most cache coherency transactions on-die. On-die communication has the benefit of both lower latency and lower power. Additionally, a shared last level cache can reduce replication.The integrated memory controller for Nehalem features up to 3 channels of DDR3 memory operating at 1.33GT/s at launch, for a total of 32GB/s peak bandwidth. The memory controller supports both registered and un-registered DDR3, but no FB-DIMMs for the mainstream implementations. Each channel of memory can operate independently and the controller services requests out-of-order to minimize latency. To take advantage of this 4x increase in memory bandwidth, each core supports up to 10 data cache misses and 16 total outstanding misses. In comparison, the Core 2 could have 8 data cache misses and 14 total misses in-flight.
Nehalem also includes an instruction set extension which spans the entire core pipeline since they impact microcode. Nehalem includes the SSE4.2 instructions, which include several instructions for string manipulations
What all this means in real terms is greater power efficiency and more speed. First indications running these new chips on pre-production, and therefore not fully optimised for the new technology, X58 based motherboards Nehalem has been showing 25% to 30% increase in performance at least in bench testing compared to similarly clock core 2 Duo chips. By the time these new motherboards and processors make the high street this increase will more than likely be higher.

Atom

Also announced at IDF were more updates and improvements to the Atom range. Although glossed over or missed by many people there are some significant improvements with lower power consumption and faster clock speeds for the Atom range of processors. This should mean new faster netbooks with longer battery life. The new Atom will feature an integrated DDR2 memory controller and Hyper Threading to.